Field of the Invention
The disclosure relates generally to circuit layouts and methods for arranging an integrated circuit, and more particularly it relates to circuit layouts and methods for arranging an integrated circuit to correct hold-time violations.
Description of the Related Art
A digital circuit design often includes a large number of sequential and combinatorial cells. A sequential cell is a circuit element that is triggered by a clock signal, e.g., a register or a latch. A combinatorial cell is a circuit element that is not triggered by a clock signal, e.g., an AND gate, an OR gate, some other type of gate, an inverter, and so on. A sequential cell typically has various timing requirements such as setup time and hold-time requirements. The setup time is the amount of time a signal is required to remain stable at a data input of the sequential cell before the arrival of a clock edge. The hold time is the amount of time the signal is required to remain stable at the sequential cell input after the arrival of the clock edge.
The combinatorial cells are typically dispersed among the synchronous cells in the circuit design. The combinatorial cells introduce delays on the signals sent between the sequential cells. If the delays through the combinatorial cells are too short, then the signals may violate hold-time requirements. Hold-time violations may also be caused by clock skew, or more generally clock edge alignment.
Many conventional circuit design tools are not able to effectively deal with hold-time violations. For example, these tools may only add a delay buffer between the cells of a signal path with hold-time violation. However, the insertion of a delay buffer between the cells of a signal path may cause the problems of power leakage, routing congestion, and routing and area penalties.
There is therefore a need in the art for techniques to fix hold-time violations in a circuit design.